1.A Low Power 8-bit Magnitude Comparator With Small Transistor Count Using STATIC CMOS Logic

作　　者：Bhaskara Rao Doddi ;B.N. Srinivasa Rao ;R. Prasad Rao

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2013 ;2(11):2836-2840.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：181208118

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2.Full Custom Design of Low Power 8-bit Magnitude Comparator With Small Transistor Count by Static Cmos

作　　者：D.Pavana kumari ;K.V.Ramana rao ;Bhaskara Rao Doddi

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2014 ;3(9):3121-3125.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：181208761

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3.Circuit Design of Low area 8-bit magnitude Comparator With Low Power by Static CMOS

作　　者：T. Suryakala ;B. Swaroopa ;Bhaskara Rao Doddi

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2015 ;4(10):3982-3986.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：181209754

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4.Area efficient Circuit Design of N-bit Carry look Ahead Adder with High Speed by using Static CMOS

作　　者：Y. Aswani ;V.Balaji ;Bhaskara Rao Doddi

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2015 ;4(10):3990-3994.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：181209756

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5.Circuit Design of Low Area 4-bit Static CMOS based DADDA Multiplier with low Power Consumption

作　　者：J. Lakshmi Aparna ;Bhaskara Rao Doddi ;Buralla Murali Krishna

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2016 ;5(3):0588-0592.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：181209953

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6.Innovative Design of CMOS 8-bit Comparator using conditional tracking for low area

作　　者：M. Meena Kumari ;Bhaskara Rao Doddi ;G.Sunil Kumar

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2017 ;6(12):1851-1855.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：215495459

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7.Design of CMOS 8-bit Comparator with Efficient VLSI Design Constraints

作　　者：Gotru Angel Priyanka ;Buralla Muralikrishna ;Bhaskara Rao Doddi

出　　处：International Journal of Innovative Research in Science, Engineering and Technology. 2016 ;5(9):15983.doi:10.15680/IJIRSET.2016.0509012

出版社：S&S Publications

文章 ID：215687835

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8.Design of 4-bit Carry look Ahead Adder with Low Area and Low Power

作　　者：Alithi Jyothi ;Earli Manemma Bhaskara Rao Doddi

出　　处：International Journal of Innovative Research in Science, Engineering and Technology. 2016 ;5(9):15990.doi:10.15680/IJIRSET.2016.0509013

出版社：S&S Publications

文章 ID：215687836

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9.Area Efficient Design of 4-Bit Carry Select Adder with Low Power

作　　者：Lekkala Ramadevi ;D.Pavana Kumari ;Bhaskara Rao Doddi

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2018 ;7(1):67-71.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：213499403

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10.Design of 4-bit Carry look Ahead Adder with Logic Gates and Cells

作　　者：M.Meena Kumari ;Bhaskara Rao Doddi ;G.Sunil Kumar

出　　处：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET). 2018 ;7(1):83-85.

出版社：Shri Pannalal Research Institute of Technolgy

文章 ID：213499406

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	Buralla Murali Krishna	1篇
	Buralla Muralikrishna	1篇
	D.Pavana Kumari	1篇
	D.Pavana kumari	1篇
	Earli Manemma Bhaskara Rao Doddi	1篇
	Gotru Angel Priyanka	1篇
	J. Lakshmi Aparna	1篇
	K.V.Ramana rao	1篇
	Lekkala Ramadevi	1篇
	M. Meena Kumari	1篇
	M.Meena Kumari	1篇
	R. Prasad Rao	1篇
	Sankara Rao Palla	1篇
	T. Suryakala	1篇
	V.Balaji	1篇
	Y E Vasanth Kumar	1篇
	Y. Aswani	1篇

	计算技术、计算机技术	10篇
	社会学	2篇

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	Bhaskara Rao Doddi	11篇
	G.Sunil Kumar	3篇
	Alithi Jyothi	1篇
	B. Swaroopa	1篇
	B.N. Srinivasa Rao	1篇

	International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)	10篇
	International Journal of Innovative Research in Science, Engineering and Technology	2篇