文章基本信息

标题：Circuit Design of Low Area 4-bit Static CMOS based DADDA Multiplier with low Power Consumption
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作者：J. Lakshmi Aparna ; Bhaskara Rao Doddi ; Buralla Murali Krishna 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2016
卷号：5
期号：3
页码：0588-0592
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Multiplier has vast applications, so designers are competing with each other if one comes up with high Speed then other one might come up with low Area like that mix of VLSI design constraints is the concern here. Till now most of the persons who has name on Multipliers had their own approach. In this paper we are intended to introduce Conditional approach in which Circuit can be designed for Logic0 Conditions or for Logic1 Conditions. Here we are not curious to get the expression and then convert that into a Cmos Circuit based on de-morgan's theorem. Transistors will be the leaf level cells in our approach in which we try to utilize each and every Demarcation line and each line gives unique Logic. We want Disadvantage of more Transistor count in CMOS to turn into somewhat less Transistor count by our Conditional approach. DADDA multiplier has been designed by using carry save adder method . The proposed approach implemented on above multiplier has been designed and simulated by using TANNER EDA Software.
关键词：staticcmos;24Tcircuit;xor;xnor