期刊名称:International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN:2278-1323
出版年度:2017
卷号:6
期号:12
页码:1851-1855
出版社:Shri Pannalal Research Institute of Technolgy
摘要:In this paper we are going to design a circuit based on conditional tracking in which we will not realize the circuit based upon the expressions but off course the circuit which we have designed will have internally some expression. We are not going to do any Boolean algebra manipulations and we will only be tracking the conditions and then convert that condition into CMOS circuit and we are going to utilize more the AOI and OAI circuits and we ensure that not more number of transistors are in series. Our design does not fix initially blocks going to be used and in our design approach whatever the blocks needed that we will be using. N-bit output can be obtained after N cell delays but speed not only depends on the number of levels but also on the hardware requirements at that levels. Maximum number of inputs in our circuits are 4 and Maximum Fan-out will be 1. Transistor reduction was achieved in range of 16% to 53% with the existing designs.our design is low area with respect to number of transistors that too in Static CMOS. Total transistor count for N-bit comparator is 6+[10*(N-1)]+10+[12*(N-1)]+4.Tanner tools are being used for schematic entry and for simulation.