文章基本信息

标题：Design of CMOS 8-bit Comparator with Efficient VLSI Design Constraints
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作者：Gotru Angel Priyanka ; Buralla Muralikrishna ; Bhaskara Rao Doddi 等
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：9
页码：15983
DOI：10.15680/IJIRSET.2016.0509012
出版社：S&S Publications
摘要：We present a Comparator with less Transistor count and low power by having less Active number ofTransistors. There are less number of Transistors in series such that by default Speed can be better. Total number oftransistor count for N-bit is (N-1)*20+6+6+4. The idea is to provide new way of Circuit Designing in Transistor levelby without even forming the equations. CMOS logic style which is being dominant in Industry is being considered fordesigning the Circuit which has the Prime Disadvantage of occupying more Area and this corresponds to number ofTransistors at the Circuit level. Total number of cells required for the Design are also very less such that it will behelpful for the Layout, though a manual or Automated Layout. Circuit which we have designed also has uniformstructure. Circuit was designed by using S-EDIT tool for Schematic entry and T-SPICE for Simulation of TANNEREDA tool.
关键词：10T BlockEven ; 10T BlockOdd; Comparator; CMOS.