文章基本信息

标题：Area Efficient Design of 4-Bit Carry Select Adder with Low Power
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作者：Lekkala Ramadevi ; D.Pavana Kumari ; Bhaskara Rao Doddi 等
期刊名称：International Journal of Advanced Research in Computer Engineering & Technology (IJARCET)
印刷版ISSN：2278-1323
出版年度：2018
卷号：7
期号：1
页码：67-71
出版社：Shri Pannalal Research Institute of Technolgy
摘要：Adder is an vital operation in ALU. Out of Many existing adders, Carry select adder have much significance. In this paper we proposed CMOS Carry select adder with low area as well as low power. We have designed a cell such that it can produce multiple outputs and this is what lead to the optimization. Universal gates like NAND and NOR also used instead of using basic logic gates like AND and OR has lead to optimization. Half sum generation unit has been optimized from 64 to 46 transistors. In Carry unit with zero carry input block transistor reduction is from 36 to 24. Carry unit with one carry input block there was limited reduction in transistor count from 42 to 36. Carry unit block has been optimized from 48 to 32 transistors. Sum unit block has not given us any scope to do optimization. Total transistor count reduction for 4-bit is from 230 to 178 with existing design and in equal proportion optimization is possible for N-bit.
关键词：CMOS; Optimization; universal gates; XNOR.