1.Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers

作　　者：Muhammad H. Rais, Syed M. Qasim

出　　处：International Journal of Computer Science and Network Security. 2010 ;10(1).

出版社：International Journal of Computer Science and Network Security

文章 ID：47404207

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2.Fpga Design and Implementation of Matrix Multiplier Architectures for Image and Signal Processing Applications

作　　者：Syed M. Qasim ;Ahmed A. Telba ;Abdulhameed Y. Almazroo

出　　处：International Journal of Computer Science and Network Security. 2010 ;10(2).

出版社：International Journal of Computer Science and Network Security

文章 ID：47750348

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3.Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA

作　　者：Muhammad H. Rais ;Syed M. Qasim

出　　处：International Journal of Computer Science and Network Security. 2009 ;9(9):59-63.

出版社：International Journal of Computer Science and Network Security

文章 ID：186858954

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4.A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box

作　　者：Muhammad H. Rais ;Syed M. Qasim

出　　处：International Journal of Computer Science and Network Security. 2009 ;9(9):305-309.

出版社：International Journal of Computer Science and Network Security

文章 ID：186858986

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5.FPGA Design and Implementation of Matrix Multiplier Architectures for Image and Signal Processing Applications

作　　者：Syed M. Qasim ;Ahmed A. Telba ;Abdulhameed Y. AlMazroo

出　　处：International Journal of Computer Science and Network Security. 2010 ;10(2):168-176.

出版社：International Journal of Computer Science and Network Security

文章 ID：186859661

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6.Efficient FPGA Realization of S-Box using Reduced Residue of Prime Numbers

作　　者：Muhammad H. Rais ;Syed M. Qasim

出　　处：International Journal of Computer Science and Network Security. 2010 ;10(1):69-74.

出版社：International Journal of Computer Science and Network Security

文章 ID：186859691

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	Syed M. Qasim	5篇
	Muhammad H. Rais	3篇
	Ahmed A. Telba	2篇
	Abdulhameed Y. AlMazroo	1篇
	Abdulhameed Y. Almazroo	1篇

	2010	4篇
	2009	2篇