文章基本信息

标题：Efficient Hardware Realization of Advanced Encryption Standard Algorithm using Virtex-5 FPGA
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作者：Muhammad H. Rais ; Syed M. Qasim
期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2009
卷号：9
期号：9
页码：59-63
出版社：International Journal of Computer Science and Network Security
摘要：This paper presents an efficient hardware realization of Rijndael Advanced Encryption Standard (AES) cryptographic algorithm using state-of-the-art Field Programmable Gate Array (FPGA). The design is coded in Very High Speed Integrated Circuit Hardware Description Language (VHDL). Timing simulation is performed to verify the functionality of the designed circuit. Performance evaluation is also done in terms of throughput and area. The design implemented on state-of-the-art Xilinx Virtex-5 (XC5VLX50FFG676-3) FPGA achieves a throughput of 4.34 Gbits/s using a total of 399 slices.
关键词：Advanced Encryption Standard (AES); FPGA; VHDL; Virtex-5