文章基本信息

标题：A Novel FPGA Implementation of AES-128 using Reduced Residue of Prime Numbers based S-Box
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作者：Muhammad H. Rais ; Syed M. Qasim
期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2009
卷号：9
期号：9
页码：305-309
出版社：International Journal of Computer Science and Network Security
摘要：In this paper, we present a novel Field Programmable Gate Array (FPGA) implementation of advanced encryption standard (AES-128) algorithm based on the design of high performance S-Box built using reduced residue of prime numbers. The objective is to present an efficient hardware realization of AES-128 using very high speed integrated circuit hardware description language (VHDL). The novel S-Box look up table (LUT) entries forms a set of reduced residue of prime number, which forms a mathematical field. The S-Box with reduced residue of prime number adds more confusion to the entire process of AES algorithm and makes it more complex and provides further resistance against attacks. The target hardware used in this paper is state-of-the-art Virtex-5 XC5VLX50 FPGA from Xilinx. The proposed design achieves a throughput of 3.09 Gbps using only 1745 slices.
关键词：Advanced Encryption Standard (AES); Very High Speed Integrated Circuit Hardware Description Language (VHDL); Field Programmable Gate Array (FPGA); Virtex-5