期刊名称：International Journal of Computer Science and Network Security
印刷版ISSN：1738-7906
出版年度：2010
卷号：10
期号：1
页码：69-74
出版社：International Journal of Computer Science and Network Security
摘要：A high performance substitution box (S-Box) implementation using reduced residue of prime numbers is presented in this paper. The byte substitution implemented using S-Box is an important part of the Advanced Encryption Standard (AES). The objective of this paper is to present an efficient Field Programmable Gate Array (FPGA) realization of S-Box using very high speed integrated circuit hardware description language (VHDL). The design was implemented on Xilinx Virtex-5 XC5VLX50 FPGA and the results obtained show that the proposed method provides an improved performance with 38% improvement in maximum clock frequency as well as efficient utilization of FPGA hardware resources.
关键词：Advanced Encryption Standard (AES); S-Box; FPGA; VHDL; Virtex-5
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