1.New Design Methodologies for High-Speed Mixed-Mode CMOS Full Adder Circuits

作　　者：Subodh Wairya ;Rajendra Kumar Nagaria ;Sudarshan Tiwari

出　　处：International Journal of VLSI Design & Communication Systems. 2011 ;2(2).

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：86826348

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2.Comparative Performance Analysis of XOR-XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

作　　者：Subodh Wairya ;Rajendra Kumar Nagaria ;Sudarshan Tiwari

出　　处：International Journal of VLSI Design & Communication Systems. 2012 ;3(2).

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：86826424

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3.Performance Evaluation of Low Power Dynamic Circuit Using Footed Diode Domino Logic

作　　者：Monika Jain ;Dr. Subodh Wairya

出　　处：International Journal of Engineering and Computer Science. 2014 ;3(10):8748-8751.

出版社：IJECS

文章 ID：144798823

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4.Performance Evaluation of Different Types of CMOS Operational Transconductance

作　　者：Vijeta ;Dr. Subodh Wairya

出　　处：International Journal of Engineering and Computer Science. 2014 ;3(10):8839-8843.

出版社：IJECS

文章 ID：144798857

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5.A 16-Bit Ripple Carry Adder Design Using High Speed Modified Feedthrough Logic

作　　者：Avinash Singh ;Dr. Subodh Wairya

出　　处：International Journal of Engineering and Computer Science. 2015 ;4(5):12058-12061.

出版社：IJECS

文章 ID：144800102

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6.A Study of Two Stage Operational Transconductance Amplifier using Floating gate MOSFET

作　　者：Vijeta ;Dr. Subodh Wairya

出　　处：International Journal of Engineering and Computer Science. 2015 ;4(10):14643-14648.doi:10.18535/ijecs/v4i10.17

出版社：IJECS

文章 ID：144800987

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7.Designing an Efficient Approach for JK and T Flip-Flop with Power Dissipation Analysis Using QCA

作　　者：Shraddha Pandey ;Sonali Singh ;Subodh Wairya

出　　处：International Journal of VLSI Design & Communication Systems. 2016 ;7(3):29.doi:10.5121/vlsic.2016.7303

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：205645900

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8.Feasible Methodology for Optimization of a Novel Reversible Binary Compressor

作　　者：Neeraj Kumar Misra ;Mukesh Kumar Kushwaha ;Subodh Wairya 等

出　　处：International Journal of VLSI Design & Communication Systems. 2015 ;6(4):1.doi:10.5121/vlsic.2015.6401

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：216765024

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9.Evolution of Structure of Some Binary Group-Based N-Bit Compartor, N-To-2N Decoder by Reversible Technique

作　　者：Neeraj Kumar Misra ;Subodh Wairya ;Vinod Kumar Singh

出　　处：International Journal of VLSI Design & Communication Systems. 2014 ;5(5):9.doi:10.5121/vlsic.2014.5502

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：216765077

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10.Performance Evaluation of Low Power Carry Save Adder for VLSI Applications

作　　者：Divya Tripathi ;Subodh Wairya

出　　处：International Journal of VLSI Design & Communication Systems. 2018 ;9(3):51.doi:10.5121/vlsic.2018.9305

出版社：Academy & Industry Research Collaboration Center (AIRCC)

文章 ID：216765103

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	Vijeta	2篇
	Amit Kumar	1篇
	Avinash Singh	1篇
	Divya Tripathi	1篇
	Monika Jain	1篇
	Mukesh Kumar Kushwaha	1篇
	Shraddha Pandey	1篇
	Sonali Singh	1篇
	Vinod Kumar Singh	1篇

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	Subodh Wairya	6篇
	Dr. Subodh Wairya	4篇
	Neeraj Kumar Misra	2篇
	Rajendra Kumar Nagaria	2篇
	Sudarshan Tiwari	2篇

	International Journal of VLSI Design & Communication Systems	6篇
	International Journal of Engineering and Computer Science	4篇