文章基本信息

标题：Fin Field Effect Transistors Performance in Analog and RF for High-k Dielectrics
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作者：D. Nirmal ; P. Vijaya Kumar
期刊名称：Defence Science Journal
印刷版ISSN：0976-464X
出版年度：2011
卷号：61
期号：3
页码：235-240
DOI：10.14429/dsj.61.695
语种：English
出版社：Defence Scientific Information & Documentation Centre
摘要：The high- k is needed to replace SiO 2 as the gate dielectric to reduce the gate leakage current. The impact of a high- k gate dielectric on the device short channel performance and scalability of nanoscale double gate Fin Field Effect Transistors (FinFET) CMOS is examined by 2-D device simulations. DG FinFETs are designed with high- k at the high performance node of the 2008 Semiconductor Industry Association International Technology Roadmap for Semiconductors (ITRS). DG FinFET CMOS can be optimally designed to yield outstanding performance with good trade-offs between speed and power consumption as the gate length is scaled to < 10 nm. Using technology computer aided design (TCAD) tools a 2-D FinFET device is created and the simulations are performed on it. The optimum value of threshold voltage is identified as VT =0.653V with e=23( ZrO 2) for the 2-D device structure. For the 2-D device structure, the leakage current has been reduced to 9.47´10-14 A. High- k improves the Ion / Ioff ratio of transistors for future high-speed logic applications and also improves the storage capability. Defence Science Journal, 2011, 61(3), pp.235-240 , DOI:http://dx.doi.org/10.14429/dsj.61.695
关键词：CMOS, FinFET, Nanoscale