文章基本信息

标题：Achieving Low Power Test Pattern By Efficient Compaction Method For SoC Design
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作者：S. Saravanan ; Har Narayan Upadhyay
期刊名称：Journal of Artificial Intelligence
印刷版ISSN：1994-5450
电子版ISSN：2077-2173
出版年度：2012
卷号：5
期号：4
页码：244-248
DOI：10.3923/jai.2012.244.248
出版社：Asian Network for Scientific Information
摘要：Present System-on-Chip (SoC) contains various design models and all the design components are integrated into single Integrated Chip (IC). Thus total volume of SoC test pattern is also growing in complex manner. This huge test pattern also invokes various challenges in switching power, memory space and accessing time. The problem on huge test pattern involved for scan based testing is focused in this research. Coloring algorithm is proposed to compact test pattern. Utilization of unspecified test pattern promises more compaction in coloring algorithm. This proposed method never contains any extra silicon area overhead. Due to this advantage, proposed technique is more suitable for reduction of test pattern. An experimental result produces significant reduction in above said problems and tested with ISCAS89 benchmark circuits.