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  • 标题:Verification and Validation Methodology for Safety Critical Embedded Systems
  • 本地全文:下载
  • 作者:P. Swaminathan
  • 期刊名称:Journal of Artificial Intelligence
  • 印刷版ISSN:1994-5450
  • 电子版ISSN:2077-2173
  • 出版年度:2012
  • 卷号:5
  • 期号:4
  • 页码:214-220
  • DOI:10.3923/jai.2012.214.220
  • 出版社:Asian Network for Scientific Information
  • 摘要:Embedded Systems used for control of the process plants can be classified as safety critical embedded systems. To achieve the specified probability failure on demand, it is essential to customize the relevant IEEE standards. Since the requirement specifications will be well specified for process control applications, it is appropriate to follow the waterfall product development cycle. Enough thoughts are not given for Verification and Validation of embedded systems. Verification and Validation process for safety critical embedded system and the challenges for Verification and Validation team are detailed in this study.
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