摘要:Digital signatures represent one of the most widely used security technologies for ensuring unforgeability and non-repudiation of digital data. In this paper a reduced power dissipation of hardware Elliptic Curve Digital Signature design has been developed. Our proposed architecture is based on the Globally Asynchronous Locally Synchronous (GALS) design methodology. In GALS system, modules that are not used frequently can be made to consume less power by pausing their local clocks until they are needed. Our design consists of using units that are clocked independently. The whole ECDSA design is captured using VHDL language, over the finite field GF (2163), and the Virtex IV FPGA device is used for the hardware implementation of the architecture