We give the first sub-exponential time deterministic polynomialidentity testing algorithm for depth-4 multilinear circuits witha small top fan-in. More accurately, our algorithm works fordepth-4 circuits with a plus gate at the top (also known as\Spsp circuits) and has a running time ofexp(\poly(log(n)log(s)k)) where n is the number ofvariables, s is the size of the circuit and k is the fan-in ofthe top gate. In particular, when the circuit is of polynomial (orquasi-polynomial) size, our algorithm runs in quasi-polynomialtime. In \cite{AgrawalVinay08}, it was shown that derandomizingpolynomial identity testing for general \Spsp circuits implies aderandomization of polynomial identity testing in generalarithmetic circuits. Prior to this work sub-exponential timedeterministic algorithms were known for depth-3 circuits withsmall top fan-in and for very restricted versions of depth-4circuits.