文章基本信息

标题：Modeling and Simulation of Data Encryption Standard Algorithm on FPGA
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作者：Shivangi Vajpayee ; Rajesh Rai
期刊名称：International Journal of Computer Technology and Applications
电子版ISSN：2229-6093
出版年度：2012
卷号：3
期号：3
页码：1015-1022
出版社：Technopark Publications
摘要：In this paper we demonstrate an efficient and compact reconfigurable hardware implementation of the Data Encryption Standard (DES) algorithm. Our design was implemented on FPGA of device VirtexEXCV400e. As a strategy to reduce the associated design critical path, we utilized a parallel structure that allowed us to compute all the eight DES S-boxes simultaneously. Our DES round design achieved a data encryption/decryption rate of 274 Mbits/s occupying only 117 CLB slices. These results are quite competitive when compared with other reported reconfigurable hardware implementations of DES.
关键词：DES; FPGA; Parallel structure