文章基本信息

标题：Static Power Optimization Using Dual Sub-Threshold Supply Voltages in Digital CMOS VLSI Circuits
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作者：K.Srilakshmi ; Y.Syamala ; A.Suvir Vikram 等
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：5
DOI：10.5121/vlsic.2013.4506
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Power dissipation in high performance systems requires more expensive packaging. In this situation, low power VLSI design has assumed great importance as an active and rapidly developing field. As the density and operating speed of CMOS VLSI chip increases, static power dissipation becomes more significant. This is due to the leakage current when the transistor is off this is threshold voltage dependent. This can be observed in the combinational and sequential circuits. Static power reduction techniques are achieved by means of operating the transistor either in Cut-off or in Saturation region completely and avoiding the clock in unnecessary circuits. In this work, "Dual sub-threshold voltage supply" technique is used to operate the transistor under off state or either in on state by applying some voltage at the gate of the MOS transistor. This static power reduction technique is to digital circuits, so that the power dissipation is reduced and the performance of the circuit is increased. The designed circuits can be simulated by using Mentor Graphics B ackend Tool.
关键词：Dual sub-threshold; reliability; power dissipation; leakage current