文章基本信息

标题：Design and Implementation of Complex Floating Point Processor Using FPGA
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作者：Murali Krishna Pavuluri ; T.S.R. Krishna Prasad ; Ch.Rambabu 等
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：5
DOI：10.5121/vlsic.2013.4504
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This paper presents complete processor hardware with three arithmetic units. The first arithmetic unit can perform 32-bit integer arithmetic operations. The second unit can perform arithmetic operations such as addition, subtraction, multiplication, division, and square root on 32-bit floating point numbers. The third unit can perform arithmetic operations such as addition, subtraction, multiplication on complex numbers. The specific advancement in this processor is the new architecture introduced for complex arithmetic unit. In general complex floating point arithmetic hardware consists of floating to fixed and fixed to floating conversions. But using such hardware will lead to compromise between accuracy and number of bits used to represent the fixed point equivalent of floating point numbers. The proposed architecture avoids that compromise and it is implemented with less number of look-up tables to save around 5500 logic gates. The complex numbers are represented using a subset of IEEE754 standard floating point format, 16-bits for real part and 16-bits for imaginary part. The floating point arithmetic unit works on 32-bit IEEE754 single precision numbers. The instruction set is specially designed to support integer, floating point and complex floating point arithmetic operations. The on-chip RAM is 8kBytes and is extendable up to 64kBytes. As the processor is designed to implement on FPGA, the embedded block RA Ms are utilized as RAM
关键词：Processor hardware; Complex floating point arithmetic hardware; look-up tables; IEEE754 standard ;floating point format; Single precision; Instruction set; On-chip RAM; and Embedded block RAM