文章基本信息

标题：Implementation of Low Area and Power Efficient Architectures for Digital FIR Filters
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作者：A.Renuka Narasimha ; K.Rajasekhar ; A.Sujana Rani 等
期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2012
卷号：2
期号：8
出版社：S.S. Mishra
摘要：Digital signal processing (DSP) i s used in w ide range of applications such as telephone, radio, video etc. Most of DSP computations involve the use of multiply accumulate operations and therefore the design of fast and power efficient multiplier is imperative. More over, the demand for portable applications of DSP architectures has dictated the need for low power & area designs. Digital Finite Impulse Response (FIR) filter has a lot of arithmetic operations. In general, arithmetic operation modules such as adder and multiplier modules, co nsume much power, energy, and circuit area. In some applications, the FIR filter circuit must be able to operate at high sample rates, while in other applications, the FIR filter circuit must be a low -power circuit operating at moderate sample rates. This paper presents the methods for implementing digital Finite Impulse Response (FIR) filter that requires optimized area and less power consumption .The methods include Modified Booth Encoding Algorithm combined with Spurious Power Suppression Technique, folding transformation in linear phase architecture, Low Pow er Digit Serial Multiplier along with carry look ahead adder, shift/add multipliers. These techniques are applied to fir filters to minimize the area and power consumptio n. The proposed designs for FIR filters have been designed using Verilog HDL and synthesized, implemented using Xilinx ISE Spartan FPGA
关键词：DSP; FIR; booth encoding; folding transformation; Xilinx ISE Spartan