文章基本信息

标题：Analysis of Network Processor Processing Elements Topologies
本地全文：下载
作者：Devesh Chaurasiya ; Pushpendra Singh ; Ankita Joshi 等
期刊名称：International Journal of Advanced Research In Computer Science and Software Engineering
印刷版ISSN：2277-6451
电子版ISSN：2277-128X
出版年度：2012
卷号：2
期号：6
出版社：S.S. Mishra
摘要：An exponential growth in high-speed requirement in computer networks due to increased number of users, servers, connections and demands for new applications, along with the tremendous growth in data traffi c has claimed the development and deployment of high-speed telecommunication systems. A solution to this problem is to use specialized processors, called network processors (NPs). These application specific instruction processors (ASIPs) are specially designed to perform packet processing task and their architecture is usually a question of different trade-offs between performance, flexibility and price. So it is therefore important to study about NPs processing elements topologies, as well as investigate which topology is efficient in terms of performance (Throughput). In this paper, we form two types of NPs processing elements topologies, parallel and pipelined topology. By analysing these two topologies our analysis indicate that pipelined topology is efficient as compared to parallel topology in terms of performance (Throughput).
关键词：Network processors; Processing elements; Parallel; Pipeline; Engine