文章基本信息

标题：Low Power CMOS Full Adder Design with 12 Transistors
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作者：Manoj Kumar ; Sandeep K. Arya ; Sujata Pandey 等
期刊名称：International Journal of Information Technology Convergence and Services (IJITCS)
印刷版ISSN：2231-1939
电子版ISSN：2231-153X
出版年度：2012
卷号：2
期号：6
出版社：AIRCC
摘要：In present work two new designs for single bit full adders have been presented using three transistors XOR gates. Adder having twelve transistors shows power consumption of 1274μW with maximum output delay of 0.2049ns. Power consumption and maximum output delay shows variation [1274 - 141.77] μW & [0.2049 – 0.4167] ns with varying supply voltage from [3.3 - 1.8] V. Further, reverse body bias technique for power reduction has been applied to adder. Adder with reverse body bias shows power consumption variations of [1270 - 1067.60] μW with varying NMOS reverse bias from [0.0 to - 2.0] V. Delay of adder shows variations [0.2049 - 0.2316] ns with reverse bias variation [0.0 to 2.0] V. Simulations have been carried out at different supply voltage with increasing reverse biased applied to NMOS transistor and results shows improvements in power consumption of adder. A comparison with earlier reported circuits have been presented and proposed circuit’s shows less power dissipation.
关键词：CMOS; Exclusive-OR (XOR); full adder; low power design and reverse body bias.