文章基本信息

标题：Efficient VLSI Architecture for 2′s Complement Based 2-D Discrete Wavelet Transform
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作者：Satyendra Tripathi ; Jitendra Jain ; Arpit Rawat 等
期刊名称：International Journal of Electronics and Computer Science Engineering
电子版ISSN：2277-1956
出版年度：2013
卷号：2
期号：2
页码：589-594
出版社：Buldanshahr : IJECSE
摘要：A 2-D discrete wavelet transform hardware design based on 2’s complement design based architecture is presented in this paper. We have proposed based on arithmetic for low complexity and efficient implementation of 2-D discrete wavelet transform. The 2’s complement design based technique has been applied to reduce the number of full adders. This architecture is suitable for high speed on-line applications, the most important one being image processing. With this architecture the speed of the 2-D discrete wavelet transform is increased. It has 100% hardware utilization efficiency.
关键词：-D Discrete wavelet transform (DWT); One; Two; Three Level; 2’s complement design scheme;Xilinx simulation.