文章基本信息

标题：A Novel Low Power Full Adder Cell
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作者：Umesha H.S. ; A.R. Aswatha
期刊名称：International Journal of Computer Science and Information Technologies
电子版ISSN：0975-9646
出版年度：2013
卷号：4
期号：4
页码：612-613
出版社：TechScience Publications
摘要：The digital systems efficiency depends on the performance of the internal components. Hence those internal components have to be designed in such a way they provide the high speed logic with low power consumption. Full Adder is one of those kinds of component which plays an important role in the design of the systems. It is one of the primary components in most of the processors also. In this paper we have proposed a Full-Adder which uses the newer architecture. The main idea is to design the CMOS based low power Full-Adder which accounts lesser area and transistor counts. The design has been carried out using the Tanner tool V13.1.
关键词：Full-Adder; Low Power; System efficiency