文章基本信息

标题：Design and Implementation of 64 Bit RISC Processor Using System on Chip (SOC)
本地全文：下载
作者：Y. B. N. V. Bhaskar ; D. Rajesh Setty ; Addanki Purna Ramesh 等
期刊名称：International Journal of Computer Science and Communication Networks
电子版ISSN：2249-5789
出版年度：2012
卷号：2
期号：1
页码：1-11
出版社：Technopark Publications
摘要：In this paper, we present the design and implementation of a 64-bit reduced instruction set (RISC) processor with built-in-self test (BIST) features. A built-in self-test (BIST) or built-in test (BIT) is a mechanism that permits a machine to test itself. Key features of the design including its architecture, data path, and instruction set are presented. The design is implemented using VERILOG and verification is done on IUS (CADENCE) simulator. The proposed design may find applications where automation and control is required, say, in bottling plants and control of robotic movements. Illustrations highlight the typical use of our processor in bottling plants using exhaustive simulations. Future applications may include its use in vending machines, ATMs, mobile phones, and Portable gaming kits
关键词：RISC; BIST; BIT; VERILOG; IUS.