文章基本信息

标题：Faster Interleaved Modular Multiplier Based on Sign Detection
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作者：Mohamed A. Nassar ; Layla A. A. El-Sayed
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2012
卷号：3
期号：1
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Data Security is the most important issue nowadays. A lot of cryptosystems are introduced to provide security. Public key cryptosystems are the most common cryptosystems used for securing data communication. The common drawback of applying such cryptosystems is the heavy computations which degrade performance of a system. Modular multiplication is the basic operation of common public key cryptosystems such as RSA, Diffie-Hellman key agreement (DH), ElGamal and ECC. Much research is now directed to reduce overall time consumed by modular multiplication operation. Abd-el-fatah et al. introduced an enhanced architecture for computing modular multiplication of two large numbers X and Y modulo given M. In this paper, a modification on that architecture is introduced. The proposed design computes modular multiplication by scanning two bits per iteration instead of one bit. The proposed design for 1024-bit precision reduced overall time by 38% compared to the design of Abd-el-fatah et al.
关键词：efficient architecture; carry-save adder; sign detection; sign estimation technique; modular multiplication;FPGA; RSA.