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  • 标题:Design and Implementation A different Architectures of mixcolumn in FPGA
  • 本地全文:下载
  • 作者:Sliman Arrag ; Abdellatif Hamdoun ; Abderrahim Tragha
  • 期刊名称:International Journal of VLSI Design & Communication Systems
  • 印刷版ISSN:0976-1527
  • 电子版ISSN:0976-1357
  • 出版年度:2012
  • 卷号:3
  • 期号:4
  • 出版社:Academy & Industry Research Collaboration Center (AIRCC)
  • 摘要:This paper details Implementation of the Encryption algorithm AES under VHDL language In FPGA by using different architecture of mixcolumn. We then review this research investigates the AES algorithm in FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Altera Quartus II software is used for simulation and optimization of the synthesizable VHDL code. The set of transformations of both Encryptions and decryption are simulated using an iterative design approach in order to optimize the hardware consumption. Altera Cyclone III Family devices are utilized for hardware evaluation.
  • 关键词:AES; Mixcolumn ; FPGA; VHDL code; encryption.
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