文章基本信息

标题：Low Power Dynamic Buffer Circuits
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作者：Amit Kumar Pandey ; Ram Awadh Mishra ; Rajendra Kumar Nagaria 等
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2012
卷号：3
期号：5
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：In this paper we propose two buffer circuits for footed domino logic circuit. It minimizes redundant switching at the output node. These circuits prevent propagation of precharge pulse to the output node during precharge phase which saves power consumption. Simulation is done using 0.18µm CMOS technology. We have calculated the power consumption, delay and power delay product of proposed circuits and compared the results with existing standard domino circuit for different logic function, loading condition, clock frequency, temperature and power supply. Our proposed circuits reduce power consumption and power delay product as compared to standard domino circuit.
关键词：Buffer; Dynamic circuit; Power consumption; Delay; Precharge pulse.