文章基本信息

标题：Design of Reversible Multipliers for Linear Filtering Applications in DSP
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作者：Rakshith Saligram ; Rakshith T.R
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2012
卷号：3
期号：6
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Multipliers in DSP computations are crucial. Thus modern DSP systems need to develop low power multipliers to reduce the power dissipation. One of the efficient ways to reduce power dissipation is by the use of bypassing technique. If a bit in the multiplier and/or multiplicand is zero the whole array of row and/or diagonal will be bypassed and hence the name bypass multipliers. This paper presents the column Bypass multiplier and 2-D bypass multiplier using reversible logic; Reversible logic is a more prominent technology, having its applications in Low Power CMOS and quantum computations. The switching activity of any component in the bypass multiplier depends only on the input bit coefficients. These multipliers find application in linear filtering FFT computational units, particularly during zero padding where there will be umpteen numbers of zeros. A bypass multiplier reduces the number of switching activities as well as the power consumption, above which reversible logic design acts to further almost nullify the dissipations.
关键词：Reversible logic; Low power Multipliers; Column Bypass multiplier; 2-D Bypass Multiplier ;Reduced;Switching Activity; Fast Fourier Transform; Zero Padding.