文章基本信息

标题：Area-Efficient Design of Scheduler for Routing Node of Network-On-Chip
本地全文：下载
作者：Rehan Maroofi ; V. N. Nitnaware ; S. S. Limaye 等
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2011
卷号：2
期号：3
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Traditional System-on-Chip (SoC) design employed shared buses for data transfer among various subsystems. As SoCs become more complex involving a larger number of subsystems, traditional bus- based architecture is giving way to a new paradigm for on-chip communication. This paradigm is called Network-on-Chip (NoC). A communication network of point-to-point links and routing switches is used to facilitate communication between subsystems. The routing switch proposed in this paper consists of four components, namely the input ports, output ports, switching fabric, and scheduler. The scheduler design is described in this paper. The function of the scheduler is to arbitrate between requests by data packets for use of the switching fabric. The scheduler uses an improved round robin based arbitration algorithm. Due to the symmetric structure of the scheduler, an area-efficient design is proposed by folding the scheduler onto itself, thereby reducing its area roughly by 50%.
关键词：Network-on-Chip; System-on-Chip; On-chip routing switch; Scheduler; iSLIP; Synthesis.