期刊名称:International Journal of VLSI Design & Communication Systems
印刷版ISSN:0976-1527
电子版ISSN:0976-1357
出版年度:2011
卷号:2
期号:3
出版社:Academy & Industry Research Collaboration Center (AIRCC)
摘要:To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm grooved- gate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS in ultralow power applications. The simulation results show that leakage contributing currents like the subthreshold current, punchthrough current and tunneling leakage current are reduced. The oxide thickness can be increased without increase in the gate induced drain leakage current, and ON-OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is reduced drastically, as well as be applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this work.