文章基本信息

标题：A 80Ms/sec 10bit PIPELINED ADC Using 1.5Bit Stages And Built-in Digital Error Correction Logic
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作者：P.Prasad Rao ; K.Lal Kishore
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2011
卷号：2
期号：3
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Use of pipelined ADCs is becoming increasingly popular both as stand alone parts and as embedded functional units in SOC design. They have acceptable resolution and high speed of operation and can be placed in relatively small area. The design is implemented in 0.18uM CMOS process. The design includes a folded cascode op-amp with a unity gain frequency of 200MHz at 88 deg. Phase margin and a dc gain of 75dB. The circuit employs a built in sample and hold circuit and a three phase non-overlapping clock.
关键词：ADC; 1.5 bit stage; CMFB; Pipeline; Redundancy bit removal algorithm