文章基本信息

标题：FPGA Implementation of Deblocking Filter Custom Instruction Hardware on NIOS - II Based SOC
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作者：Bolla Leela Naresh ; N.V.Narayana Rao ; Addanki Purna Ramesh 等
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2011
卷号：2
期号：4
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：This paper presents a frame work for hardware acceleration for post video processing system implemented on FPGA. The deblocking filter algorithms ported on SOC having Altera NIOS-II soft core processor.SOC designed with the help of SOPC builder .Custom instructions are chosen by identifying the most frequently used tasks in the algorithm and the instruction set of NIOS-II processor has been extended. Deblocking filter new instruction added to the processor that are implemented in hardware and interfaced to the NIOS- II processor. New instruction added to the processor to boost the performance of the deblocking filter algorithm. Use of custom instructions the implemented tasks have been accelerated by 5.88%. The benefit of the speed is obtained at the cost of very small hardware resources.
关键词：Deblocking filter; SOC; NIOS-II soft processor; FPGA