文章基本信息

标题：Low Power Reversible Parallel Binary Adder/Subtractor
本地全文：下载
作者：Rangaraju H G ; Venugopal U ; Muralidhara K N 等
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2010
卷号：1
期号：3
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：In recent years, Reversible Logic is becoming more and more prominent technology having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, and Optical Computing. Reversibility plays an important role when energy efficient computations are considered. In this paper, Reversible eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design III are proposed. In all the three design approaches, the full Adder and Subtractors are realized in a single unit as compared to only full Subtractor in the existing design. The performance analysis is verified using number reversible gates, Garbage input/outputs and Quantum Cost. It is observed that Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is efficient compared to Design I, Design II and existing design.
关键词：Reversible Logic; Garbage Input/output; Quantum Cost; Low Power; Reversible Parallel Binary;Adder/Subtractor.