文章基本信息

标题：Ternary Tree Asynchronous Interconnect Network for GALS' SOC
本地全文：下载
作者：Vivek E. Khetade ; S.S. Limaye
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2013
卷号：4
期号：1
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：Interconnect fabric requires easy integration of computational block operating with unrelated clocks. This paper presents asynchronous interconnect with ternary tree asynchronous network for Globally Asynchronous Locally Synchronous (GALS) system-on-chip (SOC). Here architecture is proposed for interconnection with ternary tree asynchronous network where ratio of number NOC design unit and number of router is 4:1,6:2, 8:3,10:4 etc .It is scalable for any number of NOC design unit. It offers an easy integration of different clock domain with low communication overhead .NOC design unit for GALS ‘SOC is formulated by wrapping synchronous module with input port along with input port controller, output port along with output port controller and local clock generator. It creates the interface between synchronous to asynchronous and asynchronous to synchronous. For this purpose four port asynchronous routers is designed with routing element and output arbitration and buffering with micro-pipeline. This interconnect fabric minimizes silicon area, minimize Latency and maximize throughput. Here functional model is made for TTAN and application MPEG4 is mapped on the Network .Desired traffic pattern is generated and performance of the network is evaluated. Significant improvement in the network performance parameter has been observed.
关键词：GALS; NOC; asynchronous design; ternary tree network; data synchronization