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  • 标题:2- Bit Comparator Using Different Logic Style of Full Adder
  • 本地全文:下载
  • 作者:Vandana Choudhary Rajesh Mehra
  • 期刊名称:International Journal of Soft Computing & Engineering
  • 电子版ISSN:2231-2307
  • 出版年度:2013
  • 卷号:3
  • 期号:2
  • 页码:277-279
  • 出版社:International Journal of Soft Computing & Engineering
  • 摘要:In this paper a new design of comparator is described with the help of Full adder which are the basic building block of ALU and ALU is a basic functioning unit of the microprocessors and DSP. In the world of technology it has become essential to develop various new design methodologies to reduce the power and area consumption. In this paper comparator are developed using various design of full adder. This will reduce the power of the comparator design. The proposed comparator has been designed using DSCH 3.1 and Microwind 3.1 at 120 nm technologies. The developed comparator with show an improvement of 25.14% in power.
  • 关键词:Full adder; nmos; pmos; cmos; speed; low;power; less transistor count; efficiency.
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