文章基本信息

标题：Power Optimization Technique for Pulsed Latches
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作者：P.Sreenivasulu ; K.Srinivasa Rao ; J.I.R Prakash 等
期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2013
卷号：3
期号：1
页码：290-295
出版社：International Journal of Soft Computing & Engineering
摘要：In this paper, we implement a design technique for registers used in pulsed latches in order to make leakage current low thus reducing standby power consumption. This is made by considering short or long timing path and launching or capturing register. In this work each register trades clock-to-Q delay maintaining the same timing constraints, setup time and hold time maintaining clock-to-Q delay constant for reducing the leakage current by developing three different dual threshold voltage registers. The overall reduction in the leakage current of a register can exceed 90% while maintaining the clock frequency and other design parameters such as area and dynamic power the same. This work presents an elegant methodology using pulsed latch instead of flip-flop without altering the existing design style. It reduces the dynamic power of the clock network, which can consume half of a chip's dynamic power. Real designs have shown approximately a 20 percent reduction in dynamic power using the below methodology. Three ISCAS 89 benchmark circuits are utilized to evaluate the methodology, demonstrating, on average, 23% reduction in the overall leakage current. The overall reduction in leakage current is compared for each case in different technologies. Predictive device models are used for each technology. The analysis is performed using H-SPICE.
关键词：leakage current; low leakage register design;power consumption; static power.