期刊名称:International Journal of Soft Computing & Engineering
电子版ISSN:2231-2307
出版年度:2013
卷号:2
期号:6
页码:214-219
出版社:International Journal of Soft Computing & Engineering
摘要:In this paper, we present a new Ternary logic Subtractor (TLS) that is implemented by CNTFET. In addition, we investigate the design of two Novel subtractors based on the proposed TLS. Ternary results are better than the Binary ones. Results show large decrements in delay time. Further, the second presented circuit with its Simulation results has demonstrated significant development in speed, area and power consumption. In the past extensive design techniques, Multiple-Valued Logic (MVL) circuits (especially ternary logic inverters) have been proposed by CMOS Technology. Here, the new TLS based on CNTFETs is presented, and wide simulation results have been done by HSPICE.