文章基本信息

标题：Design and Functional Verification of A SPI Master Slave Core Using System Verilog
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作者：K.Aditya ; M.Sivakumar ; Fazal Noorbasha 等
期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：2
页码：558-563
出版社：International Journal of Soft Computing & Engineering
摘要：Synchronous serial interfaces are widely used to provide economical board level interfaces between different devices such as microcontrollers, DACs ADCs and other. Many IC manufacturers produce components that are compatible with SPI and Microwire/plus. The SPI Master core is compatible with both protocols as master with some additional functionality. At the hosts side,the core acts like a Wishbone compliant slave device. The SPI master core consists of three parts, Serial interface, clock generator and Wishbone interface. The SPI core has five 32-bit registers through the Wishbone compatible interface. The serial interface consists of slave select lines, serial clock lines, as well as input and output data lines. All transfers are full duplex transfers of a programmable number of bits per transfer(upto 64 bits).It has 8 slave select lines but only one is selected at a time. We design the SPI Master-Slave core design using system verilog and do functional verification for our design in modelsim.
关键词：SPI;Wishbone;coverage.