文章基本信息

标题：Implementations of DPDE for Delay Locked Loop for High Frequency Clock of 2.5GHz High Speed Applications
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作者：J.Meenakshi ; G. Rakesh Chowdary ; A.L.G.N.Aditya 等
期刊名称：International Journal of Soft Computing & Engineering
电子版ISSN：2231-2307
出版年度：2012
卷号：2
期号：2
页码：522-527
出版社：International Journal of Soft Computing & Engineering
摘要：Variable delay elements are often used to manipulate the rising or falling edges of the clock or any other signal in integrated circuits (ICs). Delay elements are also used in delay locked loops (DLLs). Variable delay elements have many applications in VLSI circuits. They are extensively used in digital delay locked loops phase locked loops (PLLs), digitally controlled oscillators (DCOs), and microprocessor and memory circuits. In all these circuits, the variable delay element is one of the key building blocks. Its precision directly affects the overall performance of the circuit. In this a new proposed digitally controlled delay element is implemented in 130nm technology for DLL Delay locked loop for higher clock rates greater than 2.5GHz. This is implemented in Micro wind tool.
关键词：DLL; PLL; Delay element; Microprocessor;Clock frequency.