Digital waveform synthesis IC architecture - as it relates to the HP 8904A Multifunction Synthesizer - technical

Digital Waveform Synthesis IC Architecture

THE DIGITAL WAVEFORM SYNTHESIS integrated circuit (DSWIC) is a digital waveform synthesizer on an IC. It incorporates many signal generation and control functions, is cost-effective, and has multiple uses. The design objectives for the DWSIC called for the following features and functions:

* Four concurrently operating channels with independent frequency, waveform, amplitude, and phase settings

* Amplitude modulation, double-sideband suppressed carrier modulation, frequency modulation, phase modulation, and pulse modulation on one of the channels

* Channels that can be selectively summed together

* Random access memory to provide rapid selection of up to 16 different settings of frequency, amplitude, and phase under internal or external control

* Modulation of one channel from another internal channel, from the sum of channels, or from an external input.

The digital waveform synthesis IC generates one, two, or four time-multiplexed channels (A, B, C, and D) of digitally synthesized waveforms. The output of the DWSIC is converted to analog signals by means of digital-to-analog converters (DACs). Fig. 1 shows a block diagram of the DWSIC.

Control Block

The control block is the interface to a microprocessor and external control logic. With a six-bit data bus, one address line, a chip enable line, and a write enable line, the DWSIC appears to be a write-only peripheral to the controlling microprocessor. Phase reset and SYNC lines provide multiple DWSIC synchronization and fast external parameter change capabilities. The instrument clock input, CLKIN, runs at twice the required internal clock rate. The DWSIC outputs two clock signals: MODCLK and CNTOUT. MODCLK allows synchronization of external modulation inputs and data outputs, and CNTOUT is a fractional multiple of CLKIN.

A 24-bit register, PLLDIV, provides the denominator for the fractional multiply that generates the CNTOUT term. CNTOUT is the overflow from a 24-bit accumulator. The value for CNTOUT is determined by the formula: CNTOUT = CLKIN/2 X PLLDIV/2.sup.24.. The CNTOUT term is used in a phase-locked loop to lock the CLKIN term to a reference in the HP 8904A.

The channel cycle rate can be selected as a function of the CLKIN rate. A number loaded into the clock divide register allows a range of CLKIN/2 to CLKIN/2048 to be selected.

Hop RAM

The hop RAM is a 16-word-by-48-bit RAM memory that enables the DWSIC to provide frequency, phase, and/or amplitude hopping for the HP 8904A. Up to 16 settings for frequency, amplitude, and phase can entered into the hop RAM for channel A. By changing the hop RAM address via the external address lines different hop settings can be selected at a very fast rate. Internal control logic handles the enable and disable settings of the three hop parameters. For example, phase and amplitude hopping can be disabled to produce only frequency hopping without having to remove the phase and amplitude settings from the hop RAM. This feature allows the generation of frequency shift keying signals such as those used in modems, pagers, and other tone signaling devices.

Phase Accumulator

The phase accumulator is the heart of the DWSIC (see Fig. 2). There are four phase accumulators, which are each 24 bits wide and provide 0.1-Hz frequency resolution. The channel timing signals are generated by the control block described above. These signals tell the DWSIC which channel is presently active. The DWSIC can be operated in one-channel mode (only channel A active), two-channel mode (channels A and B active), or four-channel mode (channels A to D active).

Under the control of the channel signals, the phase accumulator multiplexer selects the active channel's accumulator output. This is added by the 24-bit adder to the desired frequency value coming from the FM and frequency sources. The sum, which represents the present phase value, is clocked into the sourcing channel's latch and sent to the waveform generator. The clocks for the accumulators are generated by the accumulator clock generator, which is also controlled by the channel timing signals. The phase clear signal forces the contents of all channel phase latches to zero. This permits phase initialization of all four channels.

The zero crossing logic monitors the active channel and outputs two signals: a level indicating the polarity of the present phase value, and a pulse every time it crosses zero. Both of these signals are available at the output of the DWSIC.

Phase Modulation, Amplitude Modulation, and Waveform

Generation

The phase modulation source shown in Fig. 1 provides the phase offset values that are added to the accumulated phase values from the phase accumulator for each active channel (see Fig. 3). For channel A, this source can contain additional modulation data, and by adding this data to the accumulated phase values, the phase of channel A can be modified by a fixed or varying amount. This results in a phase offset and/or phase modulation for channel A only.

The resulting phase is converted to a magnitude value by the phase-to-waveform conversion logic. This block contains mathematical logic and one quadrant of a sine lookup ROM. The resulting waveforms are sine, triangle, ramp, and square. To generate dc waveforms, a constant value of one is used. Twelve bits of an independent 31-bit pseudorandom generator are used to provide uniform noise. This same data supplied to a uniform-to-Gaussian lookup ROM generates Gaussian noise data values. Seven bits of the uniform noise data are used to generate 11 bits of Gaussian data with an eighth bit used for polarity information.

Waveform settings, which come from the control block, are used to direct the desired waveform from the waveform output multiplexer to the multiplier. The multiplier is used to provide output level control for all channels and AM and double-sideband suppressed carrier modulation for channel A. The 14 most-significant bits of a 12 X 12 bit multiplication of the waveform data are sent to the channel summer.

Channel Summation and Output

The sum select, clock, and clear control signals allow the incoming amplitude values of the time multiplexed data to be selectively added and output to the rounding logic (see Fig. 4). Sums of channels A+B, A+C, A+D, B+C, B+D, C+D, A+B+C, A+B+D, A+C+D, A+B+C+D, and (A+B) followed by (C+D) are possible. A 14-bit adder is used to maintain the accuracy of the least-significant bits. The rounding logic strips out the lower two bits and converts either the summer output or the channel amplitude to 12 bits. This value is sent to the feedback bus and outside the DWSIC via the output latches and data lines.

Four output strobes are generated by the output strobe generator to qualify data on the data lines. Each of these strobes can be individually turned off or assigned to coincide with the output data of any one of the active channels.

Modulation Sources

The three modulation source blocks shown in Fig. 1 provide the internal AM, FM, phase modulation, and pulse modulation for the DWSIC.

Frequency and FM Sources. Fig. 5 shows the FM and frequency source logic. Frequency values stored in the frequency setting registers for channels B, C, and D are output to the phase accumulator logic via the frequency multiplexer. Channel A's value consists of the sum of the frequency source multiplexer output and the output of the FM shifter. Either twenty-four bits of hop RAM data or the channel A frequency setting are selectable by the frequency source control line. The FM source control signal selects either the feedback input generated by the channel summer, the external digital modulation input, 12 bits of hop RAM data, or zero. The 12-bit output of the FM multiplexer goes into the FM shifter. This block of logic aligns the 12-bit FM data and generates the 24 bits of frequency information. Its alignment is controlled by the FM range, which represents the amount of FM deviation desired. The 24-bit result is sign-extended for the most-significant bits and zero-padded for the lower bits. When added to the frequency multiplexer output the result is either a fixed or varying frequency value for channel A.

Phase Modulation Sources. The phase modulation multiplexer shown in Fig. 6 selects the value added to the channel A phase offset setting. As determined by the phase source signal, either the feedback signal from the channel summer, the external modulation input, 12 bits of hop RAM data, or zero can be selected. This sum (channel A) or the phase offset setting of channels B, C, or D constitutes the phase modulation output of the phase multiplexer as selected by the channel signal.

AM and Pulse Modulation Source. The AM and pulse modulation source (Fig. 7) is almost identical to the phase modulation source, but has an additional pulse source multiplexer. The pulse source multiplexer selects the most-significant bit from the feedback path, external modulation input, or hop RAM and provides pulse modulation data. Pulse modulation is accomplished by allowing the 12-bit sum of the channel A amplitude setting and the desired AM modulation source to pass unchanged or be forced to zero. In the case where pulse modulation is not desired, a value of one from the pulse source multiplexer can be selected to disable the digital pulse modulator.

SYNC Latches

In series with each of the frequency, phase, amplitude, and waveform setting registers of all four channels is a set of SYNC latches. In normal operation these latches operate in a transparent mode. By special configuration of the control logic, these latches can be configured to latch the setting register values. This permits the setting registers to have new values installed without affecting the present IC configuration. At some point, if it is desired to change the DWSIC's parameters by either an internal control bit or the external SYNC control pin, the new contents of the setting registers can be latched into the latches.

Acknowledgments

Rob Dickerson, Bill Dickerson, Fred Ives, and Mike McNamee contributed to the DWSIC block diagram. Pat Owsley and John Purviance modeled the noise generation circuitry. The signaling applications expertise of Gary Johnson led to the implementation of the SYNC latches and SYNC control logic. Special thanks to Ray Fried for his enthusiastic support of this project.

COPYRIGHT 1989 Hewlett Packard Company
COPYRIGHT 2004 Gale Group