文章基本信息

标题：Design of Linear Systolic Arrays for Matrix Multiplication
本地全文：下载
作者：E. I. MILOVANOVIC ; M. K. STOJCEV ; I. Z. MILOVANOVIC 等
期刊名称：Advances in Electrical and Computer Engineering
印刷版ISSN：1582-7445
电子版ISSN：1844-7600
出版年度：2014
卷号：14
期号：1
页码：37-42
DOI：10.4316/AECE.2014.01006
出版社：Universitatea "Stefan cel Mare" Suceava
摘要：This paper presents architecture for matrix multiplication optimized to be integrated as an accelerator unit to a host computer. Two linear systolic arrays with unidirectional data flow (ULSA), used as hardware accelerators, where synthesized in this paper. The solution proposed here is designed to accelerate both the computation and communication by employing hardware address generator units (AGUs). The proposed design has been implemented on Xilinx Spartan-2E and Virtex4 FPGAs. In order to evaluate performance of the proposed solution, we have introduced quantitative and qualitative performance criteria. For the ULSA with n processing elements (PEs), the speed-up is O(n/2). Average gain factor of hardware AGUs is about 2.7, with hardware overhead of 0.6% for 32-bit PEs.