文章基本信息

标题：Karatsuba-Ofman Multiplier with Integrated Modular Reduction for GF(2m)
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作者：E. CUEVAS-FARFAN ; M. MORALES-SANDOVAL ; A. MORALES-REYES 等
期刊名称：Advances in Electrical and Computer Engineering
印刷版ISSN：1582-7445
电子版ISSN：1844-7600
出版年度：2013
卷号：13
期号：2
页码：3-10
DOI：10.4316/AECE.2013.02001
出版社：Universitatea "Stefan cel Mare" Suceava
摘要：In this paper a novel GF(2m) multiplier based on Karatsuba-Ofman Algorithm is presented. A binary field multiplication in polynomial basis is typically viewed as a two steps process, a polynomial multiplication followed by a modular reduction step. This research proposes a modification to the original Karatsuba-Ofman Algorithm in order to integrate the modular reduction inside the polynomial multiplication step. Modular reduction is achieved by using parallel linear feedback registers. The new algorithm is described in detail and results from a hardware implementation on FPGA technology are discussed. The hardware architecture is described in VHDL and synthesized for a Virtex-6 device. Although the proposed field multiplier can be implemented for arbitrary finite fields, the targeted finite fields are recommended for Elliptic Curve Cryptography. Comparing other KOA multipliers, our proposed multiplier uses 36% less area resources and improves the maximum delay in 10%.