文章基本信息

标题：FIJI: Fault InJection Instrumenter
本地全文：下载
作者：Christian Fibich ; Stefan Tauner ; Peter Rössler 等
期刊名称：EURASIP Journal on Embedded Systems
印刷版ISSN：1687-3955
电子版ISSN：1687-3963
出版年度：2019
卷号：2019
期号：1
页码：1-19
DOI：10.1186/s13639-019-0088-7
出版社：Hindawi Publishing Corporation
摘要：FPGAs are increasingly used in safety-critical applications (e.g., in aerospace and automotive engineering). Safety standards stipulate that implemented countermeasures against run-time faults such as detection and isolation of affected components, automatic reconfiguration, and redundancy mechanisms must be adequately verified. To that end, fault injection tests by various means have been established as a suitable method. For such tests, faults can be provoked by radiation, simulation, or manipulating the design, for example, by inserting additional logic or manipulating the synthesis flow. This work briefly summarizes the various fault injection approaches with a focus on methods that are capable of stressing critical nets of a design running on actual hardware without requiring to re-synthesize. While the state-of-the-art tools can work with complex designs, they often lack controllability of the exact timing of the injection events (which is important to track the system’s response on faults in a logic simulation) and/or use a high amount of FPGA resources. To overcome these issues, we propose a resource-saving netlist-based fault injection framework Fault InJection Instrumenter (FIJI) that can target individual nets at test runtime. This paper presents FIJI’s work flow, implementation details, and an evaluation in terms of FPGA resources, timing impact, and performance during instrumentation and test execution. The FIJI framework has been made publicly available by the authors under an open-source license.
关键词：Fault injection; FPGA; Safety-critical system; Verification; Electronic design automation