文章基本信息

标题：Strategies for FPGA Implementation of Non-Restoring Square Root Algorithm
其他标题：Strategies for FPGA Implementation of Non-Restoring Square Root Algorithm
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作者：Tole Sutikno ; Aiman Zakwan Jidin ; Auzani Jidin 等
期刊名称：International Journal of Electrical and Computer Engineering
电子版ISSN：2088-8708
出版年度：2014
卷号：4
期号：4
页码：548-556
语种：English
出版社：Institute of Advanced Engineering and Science (IAES)
摘要：This paper presents three strategies to implement non restoring square root algorithm based on FPGA. A new basic building block is called controlled subtract-multiplex (CSM) is introduced in first strategy which use gate level abstraction. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. Second strategy presents the first strategy in register transfer level (RTL) abstraction. In third strategy, a modification for the implementation of conventional non-restoring algorithm is presented which also use RTL abstraction. The all above strategies is implemented in VHDL programming and adopt fully pipelined architecture. The strategies have conducted to implement successfully in FPGA hardware, and each of the strategies is offer an efficient in hardware resource. In generally, the third strategy is superior.DOI:http://dx.doi.org/10.11591/ijece.v4i4.6008
其他摘要：This paper presents three strategies to implement non restoring square root algorithm based on FPGA. A new basic building block is called controlled subtract-multiplex (CSM) is introduced in first strategy which use gate level abstraction. The main principle of the method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. Second strategy presents the first strategy in register transfer level (RTL) abstraction. In third strategy, a modification for the implementation of conventional non-restoring algorithm is presented which also use RTL abstraction. The all above strategies is implemented in VHDL programming and adopt fully pipelined architecture. The strategies have conducted to implement successfully in FPGA hardware, and each of the strategies is offer an efficient in hardware resource. In generally, the third strategy is superior. DOI: http://dx.doi.org/10.11591/ijece.v4i4.6008