文章基本信息

标题：Implemenation of Vedic Multiplier Using Reversible Gates
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作者：P. Koti Lakshmi ; B Santhosh Kumar ; Prof.Rameshwar Rao 等
期刊名称：Computer Science & Information Technology
电子版ISSN：2231-5403
出版年度：2015
卷号：5
期号：13
页码：125-134
DOI：10.5121/csit.2015.51311
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：With DSP applications evolving continuously, there is continuous need for improved multiplierswhich are faster and power efficient. Reversible logic is a new and promising field whichaddresses the problem of power dissipation. It has been shown to consume zero powertheoretically. Vedic mathematics techniques have always proven to be fast and efficient forsolving various problems. Therefore, in this paper we implement Urdhva Tiryagbhyamalgorithm using reversible logic thereby addressing two important issues – speed and powerconsumption of implementation of multipliers. In this work, the design of 4x4 Vedic multiplier isoptimized by reducing the number of logic gates, constant inputs, and garbage outputs. Thismultiplier can find its application in various fields like convolution, filter applications,cryptography, and communication.
关键词：Multipliers; Urdhva Tiryagbhyam algorithm; Reversible Logic; Vedic Multiplier; Optimization;Quantum cost.