文章基本信息

标题：FPGA Based Efficient Multiplier for Image Processing Applications Using Recursive Error Free Mitchell Log Multiplier and KOM Architecture
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作者：Satish S Bhairannawar ; Rathan R ; Raja K B 等
期刊名称：International Journal of VLSI Design & Communication Systems
印刷版ISSN：0976-1527
电子版ISSN：0976-1357
出版年度：2014
卷号：5
期号：3
页码：93
DOI：10.5121/vlsic.2014.5309
出版社：Academy & Industry Research Collaboration Center (AIRCC)
摘要：The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait imagesetc., rely on multipliers to improve the quality of image. However, existing multiplication techniquesintroduce errors in the output with consumption of more time, hence error free high speed multipliers hasto be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error byintroducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliersusing radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier issynthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performanceparameters such as area utilization, speed, error and PSNR are better in the case of proposed architecturecompared to existing architectures.
关键词：Mitchell Log Multiplier; Karatsuba Ofman Multiplier; Gaussian Image Filter; PSNR; FPGA