期刊名称:International Journal of VLSI Design & Communication Systems
印刷版ISSN:0976-1527
电子版ISSN:0976-1357
出版年度:2015
卷号:6
期号:4
页码:35
出版社:Academy & Industry Research Collaboration Center (AIRCC)
摘要:The design of high performance Digital Signal Processing (DSP) Processors for Software Defined Radio(SDR) with high degree of flexibility and low power consumption has been a major challenge to thescientific community ever since its conception. The basic philosophy of SDR is to implement differentmodulation or demodulation schemes on the same underlying hardware. Currently available highperformance DSP processors, optimized with ‘Very Large Instruction Word (VLIW)’ architecture andmultiply and accumulate (MAC) units, are unable to meet the near real time speed requirements ofSoftware Defined Radios (SDR) due to their inherent sequential execution of compute intensive signalprocessing algorithms. Moreover, their power dissipation is considerably high. Even though, ApplicationSpecific Integrated Circuits (ASIC) exhibit high performance, they are also not suitable because of theirlack of flexibility. Various references on FPGA based implementations of reconfigurable architectures forSDRs are also available. However, the Look-up Table (LUT) based implementations of FPGAs are notoptimum and therefore, cannot offer highest performance at low silicon cost. Keeping this view, this paperpresents the design of a configurable communication processor for Software Defined Radio. The proposedscheme features the performance of an ASIC based design combined with the flexibility of software.Experimental results reveal that the proposed architecture has minimum hardware requirement, improvedsilicon area utilization and low power dissipation.
关键词:Field Programming Gate Array (FPGA); Software Defined Radio (SDR); Digital Signal Processing (DSP);Processor; Hardware Description language (HDL); Signal Flow Graph (SFG); Application Specific;Integrated Circuit (ASIC); Union of graph; Reconfigurable DSP Processor