文章基本信息

标题：Power Efficient Destination Address Generator of Direct Memory Access Controller in Multiprocessor SoC
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作者：Kritika M.Sharma ; Aishwarya.A ; Yasha Jyothi M Shirur 等
期刊名称：International Journal of Innovative Research in Computer and Communication Engineering
印刷版ISSN：2320-9798
电子版ISSN：2320-9801
出版年度：2017
卷号：5
期号：7
页码：13709
DOI：10.15680/IJIRCCE.2017.0507031
出版社：S&S Publications
摘要：In current scenario to meet the customer needs portable electronic devices are embedded with multipleprocessors which access the memory through controllers. Direct memory access controller[DMA] is one of the widelyused controllers in Multi Processor System on Chip[MPSoC] to access memory. Destination address generator[DAG]is one of the important blocks in the DMA controller. The VLSI trends shows that the designers are concentrating onlow power designs [1][2]. In this paper, synthesizable low power destination address register is designed andfunctionally verified. The proposed 32-bit DAG has given reduction of 38% power and 15% area when compared withconventional type of implementation.
关键词：MPSoC; DMA; DAG; Memory Management Unit (MMU); GPU; FSM; Address Generator Unit;(AGU).