文章基本信息

标题：Efficient VLSI Architecture for Sign Reversible Multiplier Circuit using DKG Gate
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作者：Deepak Kumar ; Prof. Rahul Shrivastava
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：11
页码：19410
DOI：10.15680/IJIRSET.2016.0511126
出版社：S&S Publications
摘要：Reversible rationale is all that much sought after for the future figuring advancements as they are knownnot low power dissemination having its applications in Low Power CMOS, Quantum Computing, Nanotechnology, andpicture preparing. Adders and multipliers are fundamental building blocks in many computational units. In this paperwe have presented and implemented irreversible and reversible Baugh Wooley approach using standard irreversible andreversible logic gates/cells. The problem of minimizing the number of garbage outputs is an important issue inreversible logic design. It is proved that the proposed multiplier is better and optimized, compared to its existingcounterparts with respect to the number of gates, constant inputs, garbage outputs and number of transistors required.
关键词：Irreversible Multiplier; Baugh Wooley Approach; Reversible Multiplier; Garbage Output; Quantum;Cost