文章基本信息

标题：Implementation of High Performance Area Efficient Architecture for Z-TCAM
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作者：Geethu Sabu ; Jemti Jose
期刊名称：International Journal of Innovative Research in Science, Engineering and Technology
印刷版ISSN：2347-6710
电子版ISSN：2319-8753
出版年度：2016
卷号：5
期号：9
页码：16439
DOI：10.15680/IJIRSET.2016.0509129
出版社：S&S Publications
摘要：The ternary content addressable memory (TCAM) is a type of memory that allows the memory to besearched by content rather than by address. It performs high-speed search and network routing operations in adeterministic time. The conventional TCAM circuitry has certain shortcomings compared to the RAM technology, suchas low access time, low storage capacity, high circuit complexity and high cost. Therefore, we can use the benefits ofSRAM by configuring it to behave like TCAM. A novel memory architecture based on the hybrid partitioning concept,known as the Z-TCAM, emulates the TCAM functionality with SRAM. The searching operation of data in memory andarea are the main problems that are faced by the user. It increases power consumption, cost and access time. So, thedesign can be enhanced by an area efficient implementation of the architecture and also by introducing a parity bit toboost the searching speed of SRAM based TCAM with less delay. Thus area efficient SRAM based TCAM with paritybit offers better search performance, high area efficiency, higher operating speed, lower latency and scalability. Thehybrid partitioned SRAM based TCAM architecture is verified by Verilog in ISim simulator and implemented onXilinx Spartan6.
关键词：Hybrid Partitioning (HP); Parameter extractor; Priority Encoder (PE); Static Random Access Memory;(SRAM)-based TCAM; Ternary Content Addressable Memory (TCAM )